Typically, computational hardware devices, such as general purpose processors, microcontrollers, and DSPs, will include one or more types of memory with varying memory access rates. For example, an embedded system may have digital signal processors (DSPs), where each processor may contain on-chip RAM and/or ROM memory. Furthermore, each DSP may also access external memory and the multiple DSPs may share the same external memory. On-chip memory is typically faster but smaller in size than the external memory. The size of the code and data segments of a program may be larger than the available on-chip memory of the processor that will run the program. For example, an embedded real-time program designed for the DSP may be too large to fit in the on-chip memory. As such, sections of the code and data segments of the program must be stored to external memory, and the processing unit of the DSP will read and write code and data segments from the external memory as needed. As part of deploying a program to a target processor, the code and data segments are mapped to the internal and external memory available to the processor. Since there are various types of memory with different access rates, the resulting memory mapping scheme deployed for the program can significantly impact the execution performance of the program.
To determine how to map the data and code segments of the program to the available memory resources, a detailed understanding of the algorithm implemented by the program as well as the underlying architecture of the processor is required. As such, determining a memory mapping for a program implementing a certain algorithm for a particular type of processor with various memory access rates is a challenging and difficult task. Furthermore, this can be even more daunting for systems with multiple different processors sharing memory resources. Typically, a memory mapping for a particular program to run on a certain processor and memory profile is performed manually through trial and error. This approach delivers little assurance of providing an intelligent memory mapping in a systematic way that will improve or optimize execution of the program on the processor.
In graphical modeling environments, such as a model-based design tool, block diagram models can be created to represent the design, or algorithm, of an implementation for a computational hardware device. One or more block diagram models may represent a design targeted for a single or multiple processor devices with one or more memory elements. An automatic code generation application can automatically generate code and build programs from the block diagram model to implement code for the device based on the design. In this manner, the design of a block diagram model behaves as an implementation specification for automatic code generation. However, during the code generation process, a static, default memory mapping may be specified for compiling and linking the generated code. This default memory mapping is not optimized for the execution of the program on the target device. As such, the automatic code generation application does not incorporate optimization of the memory mapping into the code generation process. The automatically generated memory mapping is optimized as a function of the given block diagram model for the specified embedded hardware platform.